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+2009-03-27.txt:21:26:08: <Deewiant> AnMaster: An SSE4.2 instruction with a separate cpuid flag
+2009-04-09.txt:21:32:15: <AnMaster> To avoid an invalid-opcode exception (#UD) on those processor implementations that do not support the CPUID instruction, software must first test to determine if the CPUID instruction is supported.
+2009-07-23.txt:12:57:32: <AnMaster> implementation. Check the status of ECX bit 0 returned by CPUID function 8000_0001h to verify that
+2009-08-09.txt:00:09:09: <AnMaster> ehird, I assume you know about CPUID btw?
+2009-08-09.txt:00:10:14: <AnMaster> however, first you must check CPUID exists. Since it didn't on 386. Thus you must first test if you can write to a specific register. If you can't bail out with "augh this is a 386. don't even try to run me"
+2009-09-26.txt:21:55:14: <fizzie> Well, it seems to read from the CPUID results (how surprising) when those are available. Though there are quite a lot of constant phys_bits settings too; like phys_bits = 36 when X86_FEATURE_PAE exists.
+2009-11-15.txt:23:00:50: <Rugxulo> it's not hard to run CPUID, besides ... P4 had SSE2 long before AMD (which is in heavy decline thanks to Core2Duo improvements)
+2009-11-15.txt:23:01:50: <Deewiant> Rugxulo: I dislike fat binaries that cpuid-switch over 8 different optimization levels. :-P
+2009-11-15.txt:23:02:01: <pikhq> Rugxulo: You don't have to run CPUID, you just build everything with SSE support.
+2009-11-22.txt:03:32:54: <zzo38> Just make a file called CPUID.COM and you can see if it works OK
+2009-11-22.txt:04:03:37: <zzo38> XOR AX,AX  CPUID  MOV AX,2424  PUSH EAX  PUSH ECX  PUSH EDX  PUSH EBX  MOV DX,SP  MOV AH,09  INT 21  XOR AX,AX  INT 21
+2009-12-10.txt:22:05:10: <zzo38> Also I noticed that the CPUID program I wrote won't work on the anarchy golf server
+2009-12-15.txt:20:54:54: <AnMaster> Deewiant, instructions very it is meaningful to have different sizes, such as mov, generally takes [bwlq]. But say stuff like cpuid doesn't
+2010-08-18.txt:12:53:09: <fizzie> Heh, CPUID strings from http://en.wikipedia.org/wiki/CPUID -- "AMDisbetter!" - early engineering samples of AMD K5 processor
+2010-08-23.txt:17:44:11: <Vorpal> to fit in the cpuid
+2010-08-23.txt:17:45:26: <Vorpal> alise, http://en.wikipedia.org/wiki/CPUID#EAX.3D0:_Get_vendor_ID
+2010-08-28.txt:11:46:51: <Vorpal> From the debug output of a JIT compiler for 68k emulation: Max CPUID level=10 Processor is GenuineIntel [PentiumPro]
+2010-08-28.txt:12:12:41: <fizzie> I think you'll need to look at the sources if you are curious enough. The CPUID model/family bits are a real mess, though.
+2010-08-28.txt:12:15:16: <fizzie> "Max CPUID level=10" probably refers to the value returned by function 0, which returns the vendor-ID ("GenuineIntel" if it's a core 2) and the largest supported standard cpuid function; 10 sounds a reasonable value there.
+2010-08-28.txt:12:28:40: <fizzie> "Intel® Processor Identification and the CPUID Instruction" application note has the CPUID family/model table, and it's about four pages with numerous footnotes, and that's only Intel's own chips.
+2010-08-28.txt:12:29:30: <fizzie> "To differentiate between the Pentium III processor, model 7 and the Pentium III Xeon processor, model 7, software should check the cache descriptor values through executing CPUID instruction with EAX = 2. If 1M or 2M L2 cache size is reported, the processor is the Pentium III Xeon processor otherwise it is a Pentium III processor or a Pentium III Xeon processor with 512-KB L2 cache size."
+2010-11-01.txt:22:05:55: <fizzie> If you want "documented", incidentally, the AMD doc 24593 (AMD64 Architecture Programmer's Manual, Volume 2: System Programming) has a "Long-Mode initialization example" assembly code snippet -- 4.5 pages, but well over half is comments -- that starts from real mode, goes to protected and from there to long. It's not the most elegant piece ever, and does things like CPUID checks for whether the long mode actually exists.
+2010-11-16.txt:17:15:11: <elliott> /CPUID style
+2010-11-16.txt:17:15:31: <elliott> Vorpal: like CPUID "GenuineIntel"
+2010-12-07.txt:20:02:51: <Vorpal> elliott, it probably checks cpuid
+2010-12-07.txt:21:38:31: <Vorpal> elliott, wait, there. That you probably need to enable embedded to remove cpuid strings
+2010-12-12.txt:03:29:33: <elliott> We have to go through real mode, check CPUID, disable the A20 line ourselves, go into protected mode, and go into long mode.
+2011-11-03.txt:20:43:48: <Vorpal> ais523\unfoog, how do you deal with CPUID?
+2011-11-06.txt:12:33:07: <twice11> CPUID is available on late 486, too.
+2011-12-31.txt:02:26:24: <zzo38> Do you know how to disable CPUID stuff for ARM processors?
+2012-06-23.txt:20:55:17: <kmc> likewise it will rewrite the code at boot according to available CPU features (e.g. choosing between CPUID and MFENCE for serialization)
+2012-08-26.txt:05:38:11: <zzo38> I do happen to think FreeDOS is OK. There are certainly problems with x86 (I don't like the existence of CPUID command is one thing, and modern extensions to the instruction set tend to confuse everything)
+2012-08-26.txt:05:44:03: <kmc> zzo38: why don't you like CPUID
+2012-08-26.txt:05:48:13: <kmc> Xen can virtualize CPUID
+2012-08-26.txt:05:49:12: <kmc> (this is a problem for code that uses CPUID as a memory barrier)
+2012-09-02.txt:16:32:52: <kmc> !c unsigned int x[4] = { 0 }; asm("cpuid" : "=b"(x[0]), "=d"(x[1]), "=c"(x[2]) : "a"(0)); printf("%s\n", (char *) x);
+2012-09-02.txt:16:35:24: <kmc> `runc int main() { unsigned int x[4] = { 0 }; asm("cpuid" : "=b"(x[0]), "=d"(x[1]), "=c"(x[2]) : "a"(0)); printf("%s\n", (char *) x); }
+2012-09-03.txt:06:31:28: <fizzie> `runc int main(void) { unsigned buf[12], i; for (i = 0; i < 3; i++) { asm("cpuid" : "=a"(buf[4*i]), "=b"(buf[4*i+1]), "=c"(buf[4*i+2]), "=d"(buf[4*i+3]) : "a"(0x80000002u+i)); } puts((char*)buf); }
+2012-12-15.txt:04:20:14: <Fiora> "Processors that provide enhanced MOVSB/STOSB operations are enumerated by the CPUID feature flag: CPUID:(EAX=7H, 
+2012-12-15.txt:04:21:49: <Fiora> instead of like having a cpuid "pshufb is atrociously slow on this cpu" flag or a "bsr/bsf are microcoded and take 15 cycles on this cpu" flag XD
+2013-01-14.txt:07:37:41: <Fiora> that almost looks like a cpuid output register
+2013-03-23.txt:00:10:22: <Jafet> cpuid and a giant table
+2013-03-23.txt:00:10:46: <kmc> many features have bits in various CPUID results
+2013-03-23.txt:00:12:04: <Bike> the SMC on cpuid conditionalizing in linux is pretty darn neat
+2013-05-04.txt:02:41:39: <kmc> "The Pentium III was the first x86 CPU to include a unique, retrievable, identification number, called PSN (Processor Serial Number). A Pentium III's PSN can be read by software through the CPUID instruction"
+2013-05-04.txt:02:52:27: <kmc> `run gccrun 'int name[12],i;for(i=0;i<3;i++){asm("cpuid":"=a"(name[4*i]),"=b"(name[4*i+1]),"=c"(name[4*i+2]),"=d"(name[4*i+3]):"a"(0x80000002+i));}puts((char*)name);'
+2013-05-04.txt:02:57:15: <Fiora> it's like, an IRC command that makes the bot print its CPUID
+2013-05-04.txt:02:57:40: <kmc> yeah i just read about this feature: http://en.wikipedia.org/wiki/CPUID#EAX.3D80000002h.2C80000003h.2C80000004h:_Processor_Brand_String
+2013-05-04.txt:02:58:06: <Fiora> I remember looking at the amd cpuid specification manual, it's like hundreds of pages long
+2013-05-04.txt:03:02:03: <Fiora> `run gccrun 'int a,b,c,d;asm("cpuid":"=a"(a),"=b"(b),"=c"(c),"=d"(d):"a"(0x80000001));}int family=((a>>8)&0xf) + ((a>>20)&0xff);int model=((a>>4)&0xf) + ((a>>12)&0xf0);printf("f:%d m:%d",family,model);'
+2013-05-04.txt:03:02:44: <zzo38> I have written a CPUID program similar to that once, in assembly language though, using the DOS DEBUG program.
+2013-05-04.txt:03:02:51: <Fiora> `run gccrun 'int a,b,c,d;asm("cpuid":"=a"(a),"=b"(b),"=c"(c),"=d"(d):"a"(0x80000001));int family=((a>>8)&0xf) + ((a>>20)&0xff);int model=((a>>4)&0xf) + ((a>>12)&0xf0);printf("f:%d m:%d",family,model);'
+2013-05-04.txt:03:10:46: <Fiora> `run gccrun 'int a,b,c,d;asm("cpuid":"=a"(a),"=b"(b),"=c"(c),"=d"(d):"a"(1));if(edx&0x00800000)puts("MMX ");if(edx&0x02000000)puts("SSE ");if(edx&0x04000000)puts("SSE2 ");if(ecx&0x00000001)puts("SSE3 ");if(ecx&0x00000200)puts("SSSE3 ");if(ecx&0x10000000)puts("AVX ");
+2013-05-04.txt:03:11:22: <Fiora> `run gccrun 'int a,b,c,d;asm("cpuid":"=a"(a),"=b"(b),"=c"(c),"=d"(d):"a"(1));if(d&0x00800000) puts("MMX ");if(d&0x02000000) puts("SSE ");if(d&0x04000000) puts("SSE2 ");if(c&0x00000001) puts("SSE3 ");if(c&0x00000200) puts("SSSE3 ");if(c&0x10000000) puts("AVX ");
+2013-05-04.txt:03:11:36: <Bike> `run gccrun 'int a,b,c,d;asm("cpuid":"=a"(a),"=b"(b),"=c"(c),"=d"(d):"a"(1));if(d&0x00800000) puts("MMX  ");if(d&0x02000000) puts("SSE ");if(d&0x04000000) puts("SSE2 ");if(c&0x00000001) puts("SSE3 ");if(c&0x00000200)  puts("SSSE3 ");if(c&0x10000000) puts("AVX ");'
+2013-05-04.txt:03:15:57: <Bike> Fiora: quick, cpuid magic to see how big pointers are!
+2013-05-04.txt:03:21:43: <Fiora> Bike: I have no idea if that's in cpuid... I guess it might be
+2013-05-04.txt:03:23:42: <Fiora> `run gccrun 'int a,b,c,d;asm("cpuid":"=a"(a),"=b"(b),"=c"(c),"=d"(d):"a"(0x80000008));printf("physical address bits: %d",a&0xff);'
+2013-05-04.txt:03:29:15: <Fiora> Bike: CPUID Fn8000_0008_EAX Long Mode Address Size Identifiers
+2013-05-04.txt:03:48:45: <shachaf> Why is cpuid suddenly not working?
+2013-05-04.txt:03:58:22: <shachaf> Why isn't the cpuid working?
+2013-05-04.txt:03:58:58: <kmc> you didn't set %eax before invoking cpuid
+2013-05-05.txt:04:42:51: <kmc> shachaf: TIL that calling CPUID from 32-bit fPIC code is tricky because the compiler reserves %ebx for the base whatever pointer
+2013-05-05.txt:04:44:27: <Fiora> I guess you could do like    push ebx; cpuid; mov ebx, %0; pop ebx;
+2013-05-05.txt:04:44:54: <kmc>     asm volatile("push %%ebx; cpuid; mov %%ebx, %0; pop %%ebx" :
+2013-05-05.txt:04:47:25: <kmc> Fiora: CPUID(EAX = 0) puts the processor brand string in EBX,EDX,ECX
+2013-05-05.txt:04:48:18: <kmc> http://en.wikipedia.org/wiki/CPUID#EAX.3D0:_Get_vendor_ID has a list
+2013-05-05.txt:04:48:43: <copumpkin> I had a cyrix "200+" back in the days when I first tinkered with cpuid
+2013-05-05.txt:04:52:57: <pikhq> push ebx; cpuid; mov ebx, eax; pop ebx
+2013-05-05.txt:05:08:57: <pikhq> kmc: Hmm. I'm not sure if there's a way to do that thing with just inline asm on x86 with only one cpuid call.
+2013-05-05.txt:05:10:57: <pikhq> push %ebx; cpuid; mov %ebx, %esi; pop %ebx // Yeah, that should work.
+2013-07-24.txt:20:55:27: <fizzie> Fiora: Apparently there's a separate "AVX-512 Conflict Detection" extension, with its own CPUID bit, that VPCONFLICT/VPLZCNT/friends comes from.
+2013-08-07.txt:00:58:23: <shachaf> `pastelogs cpuid